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The low-to-high transition generated by the first card is recognized by the interrupt controller and any subsequent transitions are ignored until the first request has been serviced. More than one ISA device may share an IRQ line as long as it is guaranteed that they never generate requests simultaneously. Since only one device may use each IRQ line, a fully-loaded machine may easily use up all of the available lines. An in-depth discussion of interrupt handling in the ISA environment may be found in the MindShare book entitled ISA System Architecture.
Slave Interrupt Controller's ELCR Bit Assignment Description 0 = IRQ15 is edge-sensitive and non-shareable, 1 = IRQ15 is levelsensitive and shareable. 0 = IRQ14 is edge-sensitive and non-shareable, 1 = IRQ14 is levelsensitive and shareable. IRQ13 is dedicated to the error output of the numeric coprocessor. This bit must be 0, selecting edge-sensitive and non-shareable. In reality, IRQ13 is shared by the numeric coprocessor and the chaining interrupt output of the DMA controller. ” 0 = IRQ12 is edge-sensitive and non-shareable, 1 = IRQ12 is levelsensitive and shareable.
Bus master one requires the use of the bus again to either complete its previously-interrupted series of transfers or to initiate a new transfer. It signals its request to the CAC by asserting MREQ1#. 9. Bus master two has finished using the bus, so it voluntarily gives up ownership by deasserting MREQ2#. 10. The CAC removes ownership from bus master two by deasserting MACK2#. 11. The CAC grants the bus to bus master one again by asserting MACK1#. Memory Refresh The EISA system board incorporates a refresh controller that requests the use of the bus once every fifteen microseconds to refresh a row of DRAM memory.