Lessons in electric circuits 4 - Digital by Tony R. Kuphaldt

By Tony R. Kuphaldt

Contents
1 NUMERATION structures 1
1.1 Numbers and emblems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 platforms of numeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Decimal as opposed to binary numeration . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Octal and hexadecimal numeration . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Octal and hexadecimal to decimal conversion . . . . . . . . . . . . . . . . . . . . . 12
1.6 Conversion from decimal numeration . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 BINARY mathematics 19
2.1 Numbers as opposed to numeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Binary addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 unfavourable binary numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.6 Bit groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3 good judgment GATES 29
3.1 electronic indications and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 The now not gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3 The ”buffer” gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4 Multiple-input gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.5 TTL NAND and AND gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.6 TTL NOR and OR gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.7 CMOS gate circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.8 Special-output gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.9 Gate universality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.10 common sense sign voltage degrees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.11 DIP gate packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.12 members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4 SWITCHES 103
4.1 change varieties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2 change touch layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.3 touch ”normal” nation and make/break series . . . . . . . . . . . . . . . . . . 111
iii
iv CONTENTS
4.4 touch ”bounce” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5 ELECTROMECHANICAL RELAYS 119
5.1 Relay building . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.2 Contactors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.3 Time-delay relays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.4 protecting relays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.5 Solid-state relays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6 LADDER common sense 135
6.1 ”Ladder” diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.2 electronic common sense capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3 Permissive and interlock circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.4 Motor regulate circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
and quite a bit more!!

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Or, more precisely, what sign of sum would necessarily indicate an overflow error? The answer to this is equally elegant: there will never be an overflow error when two numbers of opposite signs are added together! The reason for this is apparent when the nature of overflow is considered. Overflow occurs when the magnitude of a number exceeds the range allowed by the size of the bit field. The sum of two identically-signed numbers may very well exceed the range of the bit field of those two numbers, and so in this case overflow is a possibility.

0010001 . + 0010011 . --------. 01001002 . . ANSWERS: 01001002 = +3610 . 10111002 = -3610 (-1710 ) + (-1910 ) 11 1111 1101111 + 1101101 --------110111002 | Discard extra bit By using bit fields sufficiently large to handle the magnitude of the sums, we arrive at the correct answers. In these sample problems we’ve been able to detect overflow errors by performing the addition problems in decimal form and comparing the results with the binary answers. For example, when 26 CHAPTER 2. BINARY ARITHMETIC adding +1710 and +1910 together, we knew that the answer was supposed to be +3610 , so when the binary sum checked out to be -2810 , we knew that something had to be wrong.

Just as with operational amplifiers, the power supply connections to gates are often omitted in schematic diagrams for the sake of simplicity. • A truth table is a standard way of representing the input/output relationships of a gate circuit, listing all the possible input logic level combinations with their respective output logic levels. 2 The NOT gate The single-transistor inverter circuit illustrated earlier is actually too crude to be of practical use as a gate. Real inverter circuits contain more than one transistor to maximize voltage gain (so as to ensure that the final output transistor is either in full cutoff or full saturation), and other components designed to reduce the chance of accidental damage.

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