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Additional resources for Lossless realtime video compression on the Pentium III
Lossless Video Compression On Pentium III Processors Page 30 Background Intel Pentium III Processor The Intel Pentium III processor is a microarchitecural implementation of the 32bit Intel architecture [INTELARCH-OPT]. It is largely based on the Tomasulo scheme (though Intel would deny it). The use of this scheme is very much in fitting with Tomasulos original problem (since the Pentium III is still limited to 4 general purpose 32bit registers). It takes Intel architecture instructions and breaks them up into smaller micro-ops, which are then given to specific hardware units.
L2 Cache System Bus Bus Interface Unit L1 Instruction Cache L1 Data Cache Load Fetch & Decode Unit (In order unit) Fetches Instructions Decodes to micro-ops Performs branch prediction. Dispatch/Execute (out of order unit) Schedules and executes micro-ops Contains 5 execution ports Store Retirement Unit (in order unit) Retires instructions in order Writes results to registers/memory Instruction Pool/ reorder buffer L1 Instruction and Data Caches Buffer of micro-ops waiting for execution These are two seperate 16k four way set associative with a cache line length of 32 bytes.
The static Huffman tables generalise better, since they are working of differential data. 2. We are using the image context (previous pixel values) 3. Exploits lower magnitude of high frequency components in most natural images. 4. Complexity certainly lower than FELICS It is clear than the right choice is to code delta values – so I set about constructing a compressor to do just this. The first thing to do was to build a set of probability tables that emulate the probability distribution of deltas in the video.